Location: Bengaluru and Pune
Firm: Cadence
Place Description:
- Practical Verification Engineer for DDR Reminiscence Controller and PHY IP growth crew.
- The place is predicated in Bangalore.
- The position would come with purposeful verification of the DDR Reminiscence Controller and PHY IP answer of Cadence.
- The work concerned might be working with the prevailing purposeful verification setting, the addition of recent options into the verification setting, making certain varied buyer configurations are clear as a part of verification regressions, supporting clients in case of any points with utilizing the verification setting, and purposeful and code protection.
- The engineer could be accountable to make sure that the design is according to the technical and high quality necessities set for the crew – notably with respect to purposeful and code protection.
Place Necessities:
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- BE/BTech/ME/MTech – Electrical / Electronics / VLSI with expertise as a design and verification engineer, with a big portion of the latest work expertise on verification setting growth.
- Robust background in purposeful verification fundamentals, setting planning, take a look at plan era, and setting growth is a should.
- System Verilog expertise and expertise with UVM-based purposeful verification setting growth are required.
- Prior RTL Design expertise utilizing Verilog is a should – in order that the verification engineer is self-sufficient for many features of debugging.
- The Newest DDR Protocol expertise is very fascinating. Prior expertise in purposeful verification and debugging of advanced protocols is a should.
- AXI3/4 expertise is fascinating.
- Prior expertise in IP growth groups could be an added benefit.
