Cadence Design Programs, Inc. introduced the supply of the Cadence Joint Enterprise Knowledge and AI (JedAI) Platform, enabling a generational shift from single-run, single-engine algorithms in digital design automation (EDA) to algorithms that leverage huge knowledge and synthetic intelligence (AI) to optimize a number of runs of a number of engines throughout a whole SoC design and verification movement. The Cadence JedAI Platform permits engineers to glean actionable intelligence from huge volumes of chip design and verification knowledge, opening the door to a brand new era of AI-driven design and verification instruments that dramatically enhance productiveness and energy, efficiency and space (PPA). With the Cadence JedAI Platform, Cadence is unifying huge knowledge analytics throughout its AI platforms—Verisium verification, Cadence Cerebrus implementation, and Optimality system optimization—in addition to third-party silicon lifecycle administration techniques.
With the brand new Cadence JedAI Platform, engineers can seamlessly handle each structured and unstructured knowledge, together with:
- Design knowledge comparable to waveforms and protection in purposeful verification, bodily format shapes, timing/energy/voltage/variation evaluation studies, design RTL, netlist and SDC specs in design implementation
- Workload knowledge comparable to runtime, reminiscence utilization and disk area utilization, in addition to metadata concerning the inputs to every job and dependencies between them
- Workflow knowledge such because the instruments and methodology used to create a design
The Cadence JedAI Platform makes it simpler to handle design complexities related to rising customers, hyperscale computing, 5G communications, automotive and cell purposes, and extra. Prospects utilizing Cadence analogue/digital/PCB implementation, verification, and evaluation software program—and even third-party purposes—can use the Cadence JedAI Platform to unify and analyze all their huge knowledge analytics. Moreover, the brand new platform is cloud-enabled, providing extremely scalable compute sources in a safe design setting from prime cloud suppliers.
“To allow the semiconductor {industry} to proceed on its sturdy development trajectory, it’s essential that the chip design course of turns into far more environment friendly to maintain tempo with market calls for,” stated Pat Moorhead, CEO, founder and chief analyst at Moor Insights & Technique. “Enhancing design processes via AI and large knowledge analytics creates a transparent profit for engineering groups who can now extract key learnings from the huge portions of EDA knowledge proper at their fingertips. The brand new Cadence JedAI Platform is designed to supply customers with automated, clever design insights and the power to enormously scale engineering crew productiveness.”
Prospects utilizing the Cadence JedAI Platform have entry to the next advantages:
- Extremely scalable: Enterprise-grade scalability and safety, enabling design optimization throughout a number of runs, instruments, customers, designs, and EDA domains
- Actionable intelligence: Rapidly compares metrics throughout completely different variations of the identical design and/or a number of designs, offering beneficial actions to enhance PPA and improve verification protection
- Workflow administration expertise: Built-in workflow administration functionality permits customers to effectively seize chip design methodologies and routinely switch design knowledge between initiatives via knowledge connectors
- Custom-made analytics: Provides open industry-standard consumer interfaces comparable to Python, Jupyter Pocket book and REST APIs, enabling designers to create customized analytics purposes
“Assembly design targets requires a wide range of analytics and important design sources,” stated Satoshi Shibatani, director of, Digital Design Expertise Division, Shared R&D EDA Division, Renesas. “Through the use of the Cadence JedAI Platform’s huge knowledge analytics, we are able to retrieve vital data and clear up bottleneck points shortly. We’re persevering with to broaden our AI collaboration with Cadence and use our in depth knowledge successfully to our benefit to enhance PPA in addition to productiveness throughout all phases of design and verification.”
“As chip design dimension and complexity has elevated exponentially over the previous decade, the quantity of design and verification knowledge has additionally elevated with it,” stated Dr Venkat Thanvantri, VP of AI R&D at Cadence. “Beforehand, we noticed that when a chip design undertaking was accomplished, the dear knowledge was deleted to make method for the following undertaking. There are precious learnings within the legacy knowledge, and the Cadence JedAI Platform makes it simple for engineering groups to entry these learnings and apply them to future designs to ship optimum engineering productiveness and PPA and finally extra predictable, larger high quality product outcomes.”
